Graphical Design Environment for Reconfigurable Processor

The Field Programmable Processor Array (FPPA) is a new reconfigurable architecture developed by NASA/GSFC and the University of Idaho under ESTO funding. When fabricated onto a processor chip, the FPPA architecture promises high-throughput, radiationtolerant, low-power data processing, for spacecraft instruments [1]. The FPPA implements a synchronous fixed-point data flow computational model, which is not easily captured in procedural languages like C, but is easy to represent graphically. This motivates our Simulink-based design environment for the FPPA. In a process familiar to all Simulink users, the algorithm designer selects functional blocks from the menu, places them on a work screen, and connects them by drawing interconnect lines to create a FPPA data flow pipeline. A click of a button executes the data flow pipeline simulation, or translates the data flow pipeline to compiler codes, which can be used to configure the FPPA hardware. This tool will simplify programming the FPPA, suppressing architectural details.